Thesis (Ph.D., Electrical and Computer Engineering) -- University of Idaho, 2015 | A fractional-N PLL phase quantization cancellation architecture using adaptive digital delay word scaling is presented and demonstrated. A digital sign-error adaptive filter utilizing the 1-bit quantized PLL phase error and the feedback divider delta-sigma modulator accumulated error generates the optimal control word scaling for a phase cancelling digital delay. A comprehensive analytic phase noise model is derived and compared to time-domain simulation and measurement. The proposed fractional-N synthesizer, with a 2.4 GHz center frequency VCO is fabricated on a PCB with commercially available integrated circuits as a proof of concept. The synthesizer output frequency range is 144-156 MHz with 2 ppm resolution for a 20 MHz crystal oscillator reference. The adaptive phase cancellation is measured to reduce phase noise by as much as 25 dB.
